How To Reliably Protect CMOS Circuits Against Power Supply Overvoltaging
By Mike Byrne
INTRODUCTION
All IC processes have an intrinsic breakdown voltage associated wlth them. and this results in a maximum voltage stress which can be applied to any device fabricated on that process. Aa a result, all IC manufacturers give an Absolute Maximum Ratings specification for their devices. This generally gives the maximum voltage which can be applied to any of the pins on the device. Overvoltaging a device means that stresses or voltages in excess of the absolute maximum ratings are applied to the device. This application note deals in particular with overvcltage of the power supply inputs to CMOS and linear-compatible CMOS devices.
The Intrinsic breakdown voltage associated with an IC process means that a transistor, buried Zanar or other such element on the process will have a defined breakdown voltage. Obviously, if only one such element appeared between the positive supply input (Vdd) and negative power supply input (Vss) of a device, the absolute maximum rating voltage, for Vdd — Vss, would be the breakndown voltage of the element. It is not always possible to ensure that Vdd – Vss does not appear across any single element within the IC as it is often compromised by the required IC functionality, die size constraints and other factors. This means that the device manufacturer will be left with a finite voltage which can be applied across the supplies before destruction of the device results. Thus the device manufacturer will determine the limit and specify an absolute maximum rating on the data sheet for the part which is safely inside the breaktdown voltage. Users of the part must ensure that the operating voltages applied to the device are within the absolute maximum ratings. So wehere’s the problem?
POWER SUPPLY SPIKES
The problem arises, not with the steady-state value of the power supplies which is easily controlled, but with voltage spikes on the power supply lines. The most likely place for these voltage spikes to occur in most systems is during turn-on and turn-off of the power supplies. Other potential sources of voltage spikes are switching mode power supplies or when operating the devices in noisy environments, such as in the presence of large motors. During these times, depending on the output impedance of the power supplies, the load presented to the power supplies and the overall design of the power supply, the power supply voltage may significantly overshoot its nominal value and in doing so exceed the absolute maximum ratings of the device (see Figure 1).
Historically, external clamp elements such as Zener and Schottky diodes have been used to limit voltage spikes to a duration short enough to prevent any damage to the device. However, as geometries of CMOS and linear compatible CMOS processes shrink, the devices fabricated on them are getting faster. This means that in normal operation there ls a significant benefit to the user in terms of speed, bandwidth, etc. However, it also means that elements fabricated on the faster process will respond to much shorter power supply transients. It is not uncommon for devices to respond to power supply transients which are of the order of 1uS duration or less. This means that traditional methods of protecting devices using Zener and Schottky diodes no longer reliably protect the device. This is because their response time to a voltage spike or transient is now. in many cases, slower than what the device’s response time is, end therefore they do not provide any protection.
